`timescale 1ns / 1ps
module basic_4_sim1;
    reg D0,D1,D2,D3;
    reg [1:0]S;
    wire Y;
    mux41 b4(D0,D1,D2,D3,S,Y);
    initial
    begin
        D0=0;D1=0;D2=0;D3=0;S=2'b00;
        fork
            repeat (128) #5 D0=~D0;
            repeat (64) #10 D1=~D1;
            repeat (32) #20 D2=~D2;
            repeat (16) #40 D3=~D3;
            repeat (8) #80 S[0]=~S[0];
            repeat (4) #160 S[1]=~S[1];
        join
    end
    
endmodule
